Multi-processor systems, such as a symmetric multiprocessing (SMP) system, employ many parallel-operating central processing units (CPUs) which independently perform tasks under the direction of a single operating system. One type of multi-processor system is based upon a plurality of CPUs employing high-bandwidth point-to-point links (rather than a conventional shared-bus architecture) to provide direct connectivity between the CPU and to input/output (I/O) devices, memory units and/or other CPUs.
When tasks of a running application are being performed by a plurality of the multi-processor system CPUs, individual CPUs may perform various operations that require communication of information to other devices. For example, the information may be stored to a remote memory or communicated to other CPUs.
In some multi-processor systems it is desirable to use different types of CPUs. For example, a first type of CPU may be selected for performing a particular type of task for which it is well suited for, while a second type of CPU may be selected for performing another type of task for which it is well suited for.
When different types of CPUs are employed in a multiple CPU-based system, the CPUs may communicate with each other and/or communicate to other devices. As long as the CPUs and other devices, and the connecting system which couples the CPUs and the devices together, “speak” the same language, the multi-processor system will work seamlessly.
However, it is often the case that a multi-processor system will use components, such as the CPUs and/or other devices, that do not “speak” the same language. One variation between such devices occurs in the size of the cache-lines used by the various components. For example, some devices may operate under a 64 byte cache-line architecture, and other devices may operate under a 128 byte cache-line architecture. Such devices operating under different cache-line architectures can not directly communicate with each other.
Some systems solve such discrepancies between cache-line sizes by formatting data communications into a common cache-line size. Or, selected devices may be configured to convert their cache-line size to conform with a preselected standard cache-line size for the multiprocessor system architecture in which the components are deployed into. However, such solutions require extra processing power and/or time, thereby degrading the operating efficiency of the multiprocessor system.